Welcome to Hardware Modeling (191.011)

Course Team:

Dylan Baumann & Florian Huemer & Andreas Steininger & Sebastian Wiedemann

This course provides an in-depth exploration of hardware modeling, VHDL, and digital system simulation. Learn how to describe, analyze, and design hardware using modern tools.

What You'll Learn

Recognize and apply VHDL to describe hardware components.
Work with industry-standard tools like QuestaSim, Quartus, and FPGAs.
Develop testbenches and verify digital designs.
Explore timing analysis, finite state machines, and simulation techniques.

AI-Narrated Lecture Videos

Our lectures are fully automated using Tavox, a powerful open-source tool that generates AI voice-over tracks from LaTeX Beamer slides.

This allows us to create clear, structured, and consistent learning materials with text-to-speech narration.

Our innovative teaching process enables several advantages:

Maintainability: Easily update slides and have the narration adapt automatically, ensuring high quality content.
Feedback-Responsive: Quickly react to student feedback by adjusting the slides or narration, allowing continuous improvement.
Consistency: Create structured and clear learning materials with uniform narration quality.
Efficiency: Reduce manual workload, focusing on enhancing course content instead.

Interested in how it works? Check out Tavox on GitHub.

How the Course Works

The "Hardware Modeling" course combines theoretical knowledge with practical experience, utilizing modern and innovative teaching methods. The course consists of both lecture and exercise components, emphasizing flexibility and accessibility for students.

Key Innovations

Flipped Classroom with AI-Narrated Learning Videos: Students have access to learning videos, supported by self-check quizzes, allowing for flexible, self-paced learning. These videos are automatically generated using an open-source tool, Tavox, which converts text-based annotations from LaTeX Beamer slides into AI-generated voice-over videos. This approach ensures consistency, maintainability, and rapid adaptation based on student feedback.
Remote Access to Laboratory Hardware: The practical part of the course requires access to specialized hardware and software. To increase flexibility, a dedicated "Remote Lab" is available 24/7, providing students with web-based access to the necessary equipment. This allows students to conduct and test their design tasks remotely, significantly reducing the need for on-campus attendance.

Course Structure

The course is divided into three chapters, each lasting around 5-6 weeks. Every chapter includes asynchronous and synchronous phases to maximize learning flexibility:

Video Phase (Asynchronous): Students start by watching short, focused learning videos and completing quizzes to test their understanding.
Review Session (Synchronous/Optional): Voluntary review sessions allow for in-depth discussions and clarification of any uncertainties.
Exercise Phases (Asynchronous): Students work on practical design tasks, which can be done remotely via the Remote Lab with Tutor timeslots for additional support.
Exercise Sessiond (Synchronous): Small group presentations where students showcase and discuss their solutions.

The final grade consists of the performance in the exercise phases and a comprehensive exam at the end of the semester. Bonus points can be collected through various optional activities during the course.

This structure ensures a high degree of flexibility while maintaining rigorous academic standards, fostering an environment where students can learn and apply complex concepts effectively.

You can start checking out our lecture material below!

Lecture List

Introduction to Hardware Design In this lecture we will discuss what hardware modeling actually is, what makes it stand apart from writing software and why you need to care about it.
VHDL Basics In this lecture we will introduce the hardware description language VHDL, as well as some of its basic structures and their syntax.
VHDL Type System In this lecture we take a first look at the type system of VHDL. We go through commonly used basic built-in types and discuss how to define custom ones. Upcoming lectures then go into further details on composite types and other more advanced topics.
Composite Types In this lecture we take a look at composite types in VHDL and will, thus, extend our knowledge about the VHDL type system.
Describing Hardware -- Entities and Architectures Now that we have some basic knowledge about the programming language VHDL, we will take a look at how it is actually used to describe hardware.
IEEE 1164 Package In this lecture, we will introduce the \stdlogicoosf/ package, that implements the \ieee/ 1164 standard. It contains the types that are virtually always used when describing hardware in VHDL.
Numeric Standard Package In this lecture we will introduce the numeric_std package that extends the ideas about resolved types from the previous lecture to types for integer arithmetic.
Structural Modeling In this lecture we will deepen our knowledge and skills regarding practical hardware design using VHDL and structural modelling.
Behavioral Modeling In this lecture we will discuss synthesizable processes, which can be used to describe hardware using sequential statements.
Simulation and Testbenches This lecture gives an introduction on how the functionality of VHDL modules is verified using appropriate testbenches and a simulator.
Subprograms In order to facilitate reusability, maintainability, modularity and increased readability, VHDL comes with subprograms in different flavors.
Synchronous Design Style In this guest lecture you will be introduced to the synchronous design style. As we will see, this style revolves around sequential circuit elements and a global clock signal to synchronize them. The lecture will motivate why we need such synchronization.
Sequential Circuit Elements in VHDL This lecture covers how sequential circuit elements, such as flip-flops and latches, are modeled in VHDL, how they differ and how to deal with them in simulation.
Block Statements In this lecture, we will explore block statements, a useful feature in VHDL that enhances code structure and organization.
Generate Statements In this lecture, we will explore another essential class of concurrent statements: the generate statements. They are a vital tool in creating flexible and parameterized code structures, allowing designers to efficiently replicate or conditionally instantiate components based on specific parameters.
Logic Synthesis, Place and Route In this lecture we will discuss how VHDL designs become actual hardware implementations of the circuits they model. We will discuss logic synthesis, placement and routing of VHDL code to circuits. We will briefly talk about the design flow in general, and the compilation, technology mapping, placement and routing steps in particular and illustrate them at the hand of an example. We will also introduce FPGAs as a target technology for our designs.
Latches and combinational loops In this lecture we will discuss the two most common mistakes made when describing sequential circuit elements in VHDL. In particular, the structures that lead to undesired latches and combinational loops will be covered.
Advanced Testbenches In this lecture we will discuss how testbenches more powerful and with better scalability than the ones we considered so far can be written. In particular, we will look into file I/O, how random values can be generated and the standard environment package.
RAM in VHDL (for FPGAs) This lecture gives an introduction on RAM in digital design with a special focus on FPGAs. We will discuss how memory looks like in VHDL and how to interface with it.
From Circuits to Code and Back This lecture aims at giving you a more thorough understanding of how certain VHDL code structures map to hardware. We will not introduce any new language concepts and instead focus on practically applying what we already know.
Finite-State Machine Basics This lecture gives a first introduction to finite-state machines as digital circuits, their components and how they can look like in VHDL. It forms the basis for upcoming lectures on state machine modeling and implementation.
Finite-State Machine Modeling This lecture shows how finite-state machines can be modelled in general and introduces the model we use in our courses. Furthermore, we will look into two concrete examples showing how FSMs can be modelled given a description of their behavior.
Finite-State Machine Implementation (in VHDL) After watching this lecture you will know how FSMs can be implemented in VHDL. We will further present best-practices regarding the coding style and discuss some related pitfalls.
Metastability In this second guest lecture we will discuss why timing constraints in synchronous designs are important and what can happen if they are violated.
Synchronizers and Debouncers In the previous lecture you heard that external inputs can lead to the highly problematic phenomenon of metastability. In this lecture we will show you how the effects of metastability can be mitigated by using synchronizers. Furthermore, we will discuss debouncers which can be used to sanitize inputs from bouncing contacts.
Signal Assignments In this lecture we take a deeper dive into VHDL signal assignments and explore language features crucial for performing simulations requiring more complex signal timings. Understanding their semantics will also give us more insight into the event-based VHDL simulation in general.
VHDL Delay Mechanisms In this lecture we discuss the two commonly used pure and inertial delay models. We further introduce the support of VHDL for these two models via its delay mechanism.