Welcome to Hardware Modeling (191.011)

Course Team:

Dylan Baumann & Florian Huemer & Andreas Steininger & Sebastian Wiedemann

This course provides an in-depth exploration of hardware modeling, VHDL, and digital circuits simulation. Learn how to describe, analyze, and design hardware using modern tools.

What You'll Learn

Learn and apply VHDL to describe hardware components.
Work with industry-standard tools like QuestaSim, Quartus, and FPGAs.
Develop testbenches and verify digital designs using various simulation techniques.
Explore combinational circuits, the synchronous design paradigm, and finite state machines.

Lecture List

Chapter I: VHDL and hardware Design Basics

Introduction to Hardware Design thumbnail

Introduction to Hardware Design In this lecture we will discuss what hardware modeling actually is, what makes it stand apart from writing software and why you need to care about it. Abstraction Gajski Y-Chart Y-Diagram Y-Table HDL Verilog HLS Standard

VHDL Basics thumbnail

VHDL Basics In this lecture we will introduce the hardware description language VHDL, as well as some of its basic structures and their syntax.

VHDL Type System thumbnail

VHDL Type System In this lecture we take a first look at the type system of VHDL. We go through commonly used basic built-in types and discuss how to define custom ones. Upcoming lectures then go into further details on composite types and other more advanced topics.

Composite Types thumbnail

Composite Types In this lecture we take a look at composite types in VHDL and will, thus, extend our knowledge about the VHDL type system.

Circuit Description with Entities and Architectures thumbnail

Circuit Description with Entities and Architectures Now that we have some basic knowledge about the programming language VHDL, we will take a look at how it is actually used to describe hardware.

IEEE 1164 Package thumbnail

IEEE 1164 Package In this lecture, we will introduce the \stdlogicoosf/ package, that implements the \ieee/ 1164 standard. It contains the types that are virtually always used when describing hardware in VHDL.

Numeric Standard Package thumbnail

Numeric Standard Package In this lecture we will introduce the numeric_std package that extends the ideas about resolved types from the previous lecture to types for integer arithmetic.

Structural Modeling thumbnail

Structural Modeling In this lecture we will deepen our knowledge and skills regarding practical hardware design using VHDL and structural modelling.

Behavioral Modeling thumbnail

Behavioral Modeling In this lecture we will discuss synthesizable processes, which can be used to describe hardware using sequential statements.

Simulation and Testbenches thumbnail

Simulation and Testbenches This lecture gives an introduction on how the functionality of VHDL modules is verified using appropriate testbenches and a simulator.

Subprograms thumbnail

Subprograms In order to facilitate reusability, maintainability, modularity and increased readability, VHDL comes with subprograms in different flavors.